The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2022

Filed:

Jun. 19, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Il-Woo Kim, Hwaseong-si, KR;

Sang-Gi An, Hwaseong-si, KR;

Hyun-Gon Pyo, Seoul, KR;

Ik-Soo Kim, Yongin-si, KR;

Hee-Sook Park, Hwaseong-si, KR;

Ji-Woon Im, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 27/11582 (2017.01); H01L 21/311 (2006.01); H01L 27/11565 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/31111 (2013.01); H01L 27/11565 (2013.01);
Abstract

In a method of manufacturing a vertical memory device, a first sacrificial layer including a nitride is formed on a substrate. A mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer is formed. The insulation layer and the second sacrificial layer include a first oxide and a second oxide, respectively. A channel is formed through the mold and the first sacrificial layer. An opening is formed through the mold and the first sacrificial layer to expose an upper surface of the substrate. The first sacrificial layer is removed through the opening to form a first gap. A channel connecting pattern is formed to fill the first gap. The second sacrificial layer is replaced with a gate electrode.


Find Patent Forward Citations

Loading…