The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2022

Filed:

May. 10, 2021
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Deepak Ahuja, Delhi, IN;

Anchit Jain, Uttar Pradesh, IN;

Paras Mal Jain, Cupertino, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/3312 (2020.01); G06F 30/3315 (2020.01); G06F 30/396 (2020.01); G06F 30/398 (2020.01); G06F 119/12 (2020.01); G06F 119/02 (2020.01); G06F 117/04 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/3312 (2020.01); G06F 30/396 (2020.01); G06F 30/3315 (2020.01); G06F 30/398 (2020.01); G06F 2117/04 (2020.01); G06F 2119/02 (2020.01); G06F 2119/12 (2020.01);
Abstract

The technology disclosed relates to verifying metastability for a clock domain crossing (CDC) in a circuit design. The technology disclosed may include, for a destination clock domain in the circuit design, creating a circuit graph based, at least in part, on the circuit design. The circuit graph includes start points and stop points. The start points may be data inputs, clocks, and enables of the destination clock domain. The stop points may be synchronizer outputs of the destination clock domain and a source clock domain in the circuit design. The technology disclosed may also include traversing the circuit graph to mark all graph nodes that reside in a source-destination path of the CDC. Based on the marked graph nodes, the start points, and the stop points, the technology disclosed may also include propagating destination domain qualifiers on the circuit graph within an allowed sequential depth.


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