Direct cache hit and transfer in a memory sub-system that programs sequentially

Abstract

A system includes having buffers and a processing device that receives a read request with a logical block address (LBA) value for a memory device, creates a logical transfer unit (LTU) value, to include the LBA value, that is mapped to a first physical address of the memory device, and generates command tags that are to direct the processing device to retrieve data from the memory device and store the data in buffers. The command tags include a first command tag associated with the first physical address and a second command tag associated with a second physical address that sequentially follows the first physical address. The processor further creates an entry in the read cache table for the buffers. The entry can include a starting LBA value set to the first LBA value and the read offset value corresponding to the amount of data.