The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2022
Filed:
Jul. 12, 2019
Autonetworks Technologies, Ltd., Yokkaichi, JP;
Sumitomo Wiring Systems, Ltd., Yokkaichi, JP;
Sumitomo Electric Industries, Ltd., Osaka, JP;
Shungo Hiratani, Yokkaichi, JP;
Shinsuke Okumi, Yokkaichi, JP;
Arinobu Nakamura, Yokkaichi, JP;
Akira Haraguchi, Yokkaichi, JP;
AutoNetworks Technologies, Ltd., Yokkaichi, JP;
Sumitomo Wiring Systems, Ltd., Yokkaichi, JP;
Sumitomo Electric Industries, Ltd., Osaka, JP;
Abstract
Provided is a circuit board structure including a first circuit board having bus bars and a second circuit board arranged spaced apart from the first circuit board, multiple FET being arranged on the bus bars, and terminals of the multiple FETs being connected to the bus bars. The circuit board structure includes a conducting wire group sheet that covers a portion of the bus bar and is provided with multiple conducting wires that allow electricity to flow between gate terminals of the FETs and the second circuit board. The semiconductor element FETs, which are arranged side by side, are provided such that the gates terminals are arranged in the same direction with respect to the direction in which the semiconductor element FETs are arranged side by side.