The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2022
Filed:
Feb. 11, 2021
Bae Systems Information and Electronic Systems Integration Inc., Nashua, NH (US);
Jason F. Ross, Haymarket, VA (US);
BAE Systems Information and Electronic Systems Integration Inc., Nashua, NH (US);
Abstract
A level shifting circuit, the circuit comprising a VL input; an I/O VL; a VCC input; an I/O VCC; a first pull-up resistor disposed between the VL input and I/O VL; a second pull-up resistor disposed between the VCC input and I/O VCC; a first pull-up assist circuit comprising a first pull-up assist p-channel MOSFET having a source/body, drain, and gate, the source/body and drain being connected to VL and I/O VL; a second pull-up assist circuit comprising a second pull-up assist p-channel MOSFET having a source/body, drain, and gate, the source/body and drain being connected to VCC and I/O VCC, respectively; a pass-gate n-channel MOSFET in operative communication with I/O VL, I/O VCC, and VL, the pass-gate being configured to reduce the voltage level of a signal driven from I/O VCC to the voltage level of I/O VL; and a one-shot circuit configured to detect a I/O VL or I/O VCC transition from a low state to a high state, to produce a pulse in response thereto, and to communicate that pulse to the gates of the first and second pull-up assist p-channel MOSFETs, wherein the second pull-up resistor is configured to increase the voltage level of a signal driven from I/O VL to the voltage level of I/O VCC.