The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2022

Filed:

Feb. 11, 2019
Applicant:

Nexperia B.v., Nijmegen, NL;

Inventors:

Hans-Martin Ritter, Hamburg, DE;

Frank Burmeister, Hamburg, DE;

Assignee:

Nexperia B.V., Nijmegen, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 23/62 (2006.01); H01L 23/373 (2006.01); H01L 21/84 (2006.01); H01L 21/762 (2006.01); H01L 27/02 (2006.01); H01L 29/861 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/76283 (2013.01); H01L 21/84 (2013.01); H01L 23/3735 (2013.01); H01L 23/62 (2013.01); H01L 27/0248 (2013.01); H01L 27/0255 (2013.01); H01L 29/66121 (2013.01); H01L 29/861 (2013.01); H01L 2224/83193 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01);
Abstract

A semiconductor device structure and method of manufacturing a semiconductor device is provided. The method includes providing a first semiconductor substrate having a first major surface and an opposing second major surface, the first major surface having a first metal layer formed thereon; providing a second semiconductor substrate having a first major surface and an opposing second major surface, with the second semiconductor substrate including a plurality of active device regions formed therein and a second metal layer formed on the first major surface connecting each of the plurality of active device regions; bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate; and forming device contacts on the second major surface of the second semiconductor substrate for electrical connection to each of the plurality of active device regions.


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