The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2022

Filed:

Jul. 20, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yu-Wen Tseng, Chiayi, TW;

Tsung-Yu Yang, Tainan, TW;

Chung-Jen Huang, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/00 (2006.01); G11C 16/10 (2006.01); G11C 16/04 (2006.01); H01L 27/11521 (2017.01); G11C 16/14 (2006.01); H01L 27/11526 (2017.01); H01L 29/788 (2006.01); H01L 27/11524 (2017.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/0433 (2013.01); G11C 16/14 (2013.01); H01L 27/11521 (2013.01); H01L 27/11524 (2013.01); H01L 27/11526 (2013.01); H01L 29/42328 (2013.01); H01L 29/7881 (2013.01); G11C 2216/04 (2013.01);
Abstract

A memory unit includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, floating gate structures select gates, a common source and drains. The common source is disposed in the substrate, and the erase gate structure is disposed on the common source. The floating gate structures protrude from recesses of the substrate at two opposite sides of the erase gate structure. A method for controlling the memory unit includes applying an erase gate programming voltage on the erase gate structure, applying a control gate programming voltage on the common source, applying a bit line programming voltage on the drains, and applying word line programming voltage on the select gates, in which the control gate programming voltage is greater than the erase gate programming voltage.


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