The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2022

Filed:

May. 27, 2020
Applicants:

Jiangsu Advanced Memory Technology Co., Ltd., Huaian, CN;

Jiangsu Advanced Memory Semiconductor Co., Ltd., Huaian, CN;

Alto Memory Technology Corporation, Zhubei, TW;

Inventors:

Yu-Cheng Liao, Zhubei, TW;

Chun-Chih Liu, Zhubei, TW;

Ching-Sung Chiu, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 14/00 (2006.01); G11C 13/00 (2006.01); G11C 11/419 (2006.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
G11C 14/009 (2013.01); G11C 11/412 (2013.01); G11C 11/419 (2013.01); G11C 13/004 (2013.01); G11C 13/0004 (2013.01); G11C 13/0028 (2013.01); G11C 13/0069 (2013.01);
Abstract

A mixed mode memory comprises a memory array, a word line decoder, an intermediary circuit and a reading and writing circuit, wherein the word line decoder is electrically coupled to the memory array, and the intermediary circuit is electrically coupled to the memory array and the writing circuit. The memory array comprises mixed mode memory cells with each cell comprising a reading and writing component group, a storage circuit and a selection circuit. The reading and writing component group is electrically coupled to a word line which controls the reading and writing component group to be conducted or not conducted, and electrically coupled to two bit lines which respectively transmit two data signals. The storage circuit generates two reading response signals based on a reading drive signal. The selection circuit controls the storage circuit to operate in a volatile or non-volatile storage mode based on a selection voltage.


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