The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11341310 B1

Date of Patent:

May. 24, 2022

Filed:

Nov. 13, 2020

Layout-versus-schematic (lvs) debugging and error diagnosis via type of graph matching

Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Chiu-Yu Ku, Taipei, TW;

Wei-Shun Chuang, Taipei, TW;

Chia-Wei Hsu, Taipei, TW;

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:

Sterne, Kessler, Goldstein & Fox P.L.L.C.

Primary Examiner:

Naum Levin

Int. Cl.

CPC ...

G06F 30/00 (2020.01); G06F 30/398 (2020.01); G06F 30/327 (2020.01); G06F 30/392 (2020.01);

U.S. Cl.

CPC ...

G06F 30/398 (2020.01); G06F 30/327 (2020.01); G06F 30/392 (2020.01);

Abstract

A method is disclosed including analyzing a layout netlist including a first set of nodes against a schematic netlist including a second set of nodes. Each node of the first and second sets of nodes is assigned a matching type for identifying matching nodes between the first and second sets of nodes. The method includes determining one or more unmatched nodes between the first set of nodes and the second set of nodes based on the matching type. The method includes generating a convergence graph comprising nodes of the first set of nodes that have a corresponding matching node in the second set of nodes based on the matching type, and the one or more unmatched nodes.

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