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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11341308 B1

PDFFull Text
Date of Patent:
May. 24, 2022

Filed:

Feb. 18, 2021

Method and layout of an integrated circuit

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Mahantesh Hanchinal, Hsinchu, TW;

Shu-Yi Ying, Hsinchu, TW;

Chi Wei Hu, Hsinchu, TW;

Min-Yuan Tsai, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

Hauptman Ham, LLP

Primary Examiner:

Phallaka Kik

Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 30/3953 (2020.01); G06F 30/3947 (2020.01); G03F 1/36 (2012.01); H01L 21/027 (2006.01); H01L 21/768 (2006.01); H01L 21/76 (2006.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G03F 1/36 (2013.01); G06F 30/398 (2020.01); H01L 21/027 (2013.01); H01L 21/76895 (2013.01); G06F 30/3947 (2020.01); G06F 30/3953 (2020.01); G06F 2119/18 (2020.01); Y02P 90/02 (2015.11);
Abstract

A method of manufacturing an integrated circuit includes generating a layout of a first and a second cell, adjusting a first spacing between an adjacent pair of routing tracks in a first set of routing tracks to be equal to a second spacing, adjusting a third spacing between an adjacent pair of routing tracks in a second set of routing tracks to be equal to a fourth spacing, placing a first pair of conductive patterns on the first set of routing tracks, placing a second pair of conductive patterns on the second set of routing tracks, forming a first set of conductive structures based on the first pair of conductive patterns, and forming a second set of conductive structures based on the second pair of conductive patterns. The first and second cell have a same cell height that is a non-integer multiple of a minimum pitch.

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