The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2022

Filed:

Oct. 01, 2020
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Mehran Mohammadi Izad, San Jose, CA (US);

Aida Varzaghani, Mountain View, CA (US);

Bardia Bozorgzadeh, San Jose, CA (US);

Stefanos Sidiropoulos, Palo Alto, CA (US);

Assignee:

CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); G06F 11/16 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1604 (2013.01); G06F 1/10 (2013.01);
Abstract

An IC chip can include a buffer and correction module that receives a set of multiphase clock signals at a given frequency, the buffer and correction module can include a differential skew detector that detects a skew between signals of the set of multiphase clock signals. The skew detector can include a set of SR latches. Differential clock signals of the set of multiphase clock signals are input into each SR latch, and the differential clock signals of the set of multiphase clock signals are set to be 180 degrees out of phase. A voltage difference between a DC component of a first output signal and a DC component of a second output signal of a respective SR latch in the set of SR latches varies as a function of the skew between the differential clock signals of the set of multiphase clock signals.


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