The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2022

Filed:

Nov. 19, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chia-Cheng Ho, Hsinchu, TW;

Hui-Ting Lu, Zhudong Township, TW;

Pei-Lun Wang, Zhubei, TW;

Yu-Chang Jong, Hsinchu, TW;

Jyun-Guan Jhou, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 21/765 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/402 (2013.01); H01L 21/28088 (2013.01); H01L 21/765 (2013.01); H01L 21/823842 (2013.01); H01L 27/0922 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); H01L 29/66681 (2013.01); H01L 29/7816 (2013.01);
Abstract

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a source region and a drain region within a substrate. A drift region is formed within the substrate such that the drift region is disposed laterally between the source region and the drain region. A first gate structure is formed over the drift region. An inter-level dielectric (ILD) layer is formed over the first gate structure. The ILD layers is patterned to define a field plate opening. A first field plate layer, a second field plate layer, and a third field plate layer are formed within the field plate opening.


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