The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2022

Filed:

May. 08, 2020
Applicants:

National Institute of Advanced Industrial Science and Technology, Tokyo, JP;

Wacom R&d Corporation, Tokyo, JP;

Inventors:

Shigeki Sakai, IbarakI, JP;

Mitsue Takahashi, Ibaraki, JP;

Masaki Kusuhara, Tokyo, JP;

Masayuki Toda, Tokyo, JP;

Masaru Umeda, Tokyo, JP;

Yoshikazu Sasaki, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); G11C 11/22 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01); H01L 27/1159 (2017.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/40111 (2019.08); G11C 11/223 (2013.01); H01L 21/022 (2013.01); H01L 21/02181 (2013.01); H01L 21/02197 (2013.01); H01L 21/02266 (2013.01); H01L 21/02271 (2013.01); H01L 21/02337 (2013.01); H01L 21/02356 (2013.01); H01L 29/513 (2013.01); H01L 29/516 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H01L 27/1159 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01);
Abstract

A FeFET and a method of its manufacture are provided, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm<dr<150 nm, without impairing the data retention property of not less than 10seconds and the data rewrite endurance property of not less than 10times, of those that have hitherto been developed, and the FeFET allowing a memory window of 0.40 V or more when a sweep amplitude of the gate voltage is not more than 3.3 V.


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