The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2022

Filed:

Oct. 21, 2020
Applicant:

Nexperia B.v., Nijmegen, NL;

Inventor:

Steven Peake, Nijmegen, NL;

Assignee:

Nexperia B.V., Nijmegen, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/07 (2006.01); H01L 21/8234 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0727 (2013.01); H01L 21/823418 (2013.01); H01L 21/823462 (2013.01); H01L 21/823475 (2013.01); H01L 29/401 (2013.01); H01L 29/41775 (2013.01); H01L 29/4236 (2013.01);
Abstract

This disclosure relates to a combined MOS controlled diode (MCD) and MOS transistor semiconductor device and associated method of manufacture. The semiconductor device includes an epitaxial semiconductor layer arranged on a semiconductor substrate and a matrix of trenches formed in the epitaxial layer, with the matrix of trenches including a first plurality of spaced apart parallel trenches and a second plurality of spaced apart parallel trenches. Each of the first plurality of parallel trenches is orthogonal to each of the second plurality of parallel trenches and gate electrodes are arranged in each of the first plurality of spaced apart parallel trenches. Source electrodes are arranged in each of the second plurality of spaced apart parallel trenches.


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