The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2022

Filed:

Jul. 27, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Bang-Tai Tang, New Taipei, TW;

Tai-Chun Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/3115 (2006.01); H01L 29/423 (2006.01); H01L 21/8234 (2006.01); H01L 27/12 (2006.01); H01L 21/768 (2006.01); H01L 21/3215 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28247 (2013.01); H01L 21/022 (2013.01); H01L 21/0217 (2013.01); H01L 21/0228 (2013.01); H01L 21/02211 (2013.01); H01L 21/02321 (2013.01); H01L 21/02337 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/32134 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 21/3115 (2013.01); H01L 21/31155 (2013.01); H01L 21/32155 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 21/76897 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01); H01L 27/1288 (2013.01); H01L 29/42312 (2013.01); H01L 29/7848 (2013.01);
Abstract

A semiconductor device and a method of forming the semiconductor device are disclosed. A method includes forming a gate stack over a semiconductor structure. The gate stack is recessed to form a first recess. A first dielectric layer is formed along a bottom and sidewalls of the first recess, the first dielectric layer having a first etch rate. A second dielectric layer is formed over the first dielectric layer, the second dielectric layer having a second etch rate, the first etch rate being higher than the second etch rate. A third dielectric layer is formed over the second dielectric layer. An etch rate of a portion of the third dielectric layer is altered. The first dielectric layer, the second dielectric layer, and the third dielectric layer are recessed to form a second recess. A capping layer is formed in the second recess.


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