The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2022
Filed:
Oct. 01, 2020
Cadence Design Systems, Inc., San José, CA (US);
Nan Zhang, Andover, MA (US);
Chandrashekar L. Chetput, San Jose, CA (US);
Aaron Mitchell Spratt, Uxbridge, MA (US);
Joseph Leo Zielke, Jr., Doylestown, PA (US);
Rajat Kanti Mitra, Bedford, MA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
The present disclosure relates to a computer-implemented method for mixed signal design verification. Embodiments may include receiving, using a processor, an electronic circuit design and compiling and elaborating the electronic circuit design. Embodiments may also include simulating the electronic circuit design and updating, during the simulating, a System Verilog User-Defined Resolution function ('SV-UDR') associated with the electronic circuit design.