The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2022

Filed:

Dec. 23, 2020
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Gamal Refai-Ahmed, Santa Clara, CA (US);

Chi-Yi Chao, New Taipei, TW;

Huayan Wang, Campbell, CA (US);

Suresh Ramalingam, Fremont, CA (US);

Volker Aue, Dresden, DE;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/20 (2006.01); H05K 1/02 (2006.01); H01Q 1/00 (2006.01);
U.S. Cl.
CPC ...
H05K 7/2049 (2013.01); H01Q 1/002 (2013.01); H05K 1/0204 (2013.01); H05K 1/0209 (2013.01); H05K 1/0243 (2013.01);
Abstract

An electronic device is provided that balances the force applied to temperature control elements such that stress within components of the electronic device can be effectively managed. In one example, an electronic device is provided that includes a printed circuit board (PCB), a chip package, a thermal management system, a thermal spreader, and first and second biasing members. The chip package is mounted to the PCB. The thermal management system and spreader are disposed the opposite of the chip package relative to the PCB. The first biasing member is configured to control a first force sandwiching the chip package between the thermal spreader and the PCB. The second biasing member is configured to control a second force applied by the thermal management system against the thermal spreader. The first force can be adjusted separately from the second force so that total forces applied to the chip package and PCB may be effectively balanced.


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