The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2022

Filed:

May. 13, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Chetan Chauhan, Folsom, CA (US);

Sourabh Dongaonkar, Santa Clara, CA (US);

Rajesh Sundaram, Folsom, CA (US);

Jawad Khan, Portland, OR (US);

Sandeep Guliani, Folsom, CA (US);

Dipanjan Sengupta, Hillsboro, OR (US);

Mariano Tepper, Santa Clara, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 16/27 (2019.01);
U.S. Cl.
CPC ...
G06F 12/0207 (2013.01); G06F 16/278 (2019.01);
Abstract

Technologies for media management for providing column data layouts for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The circuitry is configured to store a data cluster of a logical matrix in the column-addressable memory with a column-based format and to read a logical column of the data cluster from the column-addressable memory with a column read operation. Reading the logical column may include reading logical column data diagonally from the column-address memory, including reading from the data cluster and a duplicate copy of the data cluster. Reading the logical column may include reading from multiple complementary logical columns. Reading the logical column may include reading logical column data diagonally with a modulo counter. The column data may bread from a partition of the column-address memory selected based on the logical column number. Other embodiments are described and claimed.


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