The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2022
Filed:
Dec. 13, 2018
No.24 Research Institute of China Electronics Technology Group Corporation, Chongqing, CN;
Jie Pu, Chongqing, CN;
Gangyi Hu, Chongqing, CN;
Dongbing Fu, Chongqing, CN;
Zhengping Zhang, Chongqing, CN;
Liang Li, Chongqing, CN;
Ting Li, Chongqing, CN;
Daiguo Xu, Chongqing, CN;
Mingyuan Xu, Chongqing, CN;
Xiaofeng Shen, Chongqing, CN;
Xianjie Wan, Chongqing, CN;
Youhua Wang, Chongqing, CN;
Abstract
The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.