The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Apr. 20, 2021
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Masafumi Nakatani, Yokohama, JP;

Hiroki Murakami, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B 5/04 (2006.01); G05F 3/26 (2006.01); H03K 3/0232 (2006.01); H03K 3/011 (2006.01); H03K 3/0231 (2006.01); G05F 1/573 (2006.01); H03K 5/135 (2006.01); G05F 1/56 (2006.01);
U.S. Cl.
CPC ...
H03B 5/04 (2013.01); G05F 1/561 (2013.01); G05F 1/573 (2013.01); G05F 3/26 (2013.01); G05F 3/262 (2013.01); H03K 3/011 (2013.01); H03K 3/0231 (2013.01); H03K 3/0232 (2013.01); H03K 5/135 (2013.01);
Abstract

The present invention provides an oscillator circuit and a semiconductor integrated circuit, which can suppress the upper limit of the frequency of a clock signal due to an error of the constant current circuit. The oscillator circuit of the present invention includes a constant current circuit, an oscillator, and a current limiting circuit. The constant current circuit generates a first output current according to a supply voltage. The current limiting circuit receives the first output current and generates a second output current, and establishes an upper limit for the second output current when the supply voltage drops below a lower limit of a guaranteed operational range of the constant current circuit. The oscillator generates a clock signal according to the second output current. By establishing the upper limit for the second output current, the upper limit of the frequency of the clock signal can be suppressed.


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