The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Jan. 30, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Sunglyong Kim, Allen, TX (US);

Seetharaman Sridhar, Richardson, TX (US);

Sameer Pendharkar, Allen, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/28 (2006.01); H03K 17/687 (2006.01); H01L 29/10 (2006.01); H01L 21/761 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 27/07 (2006.01); H01L 29/08 (2006.01); H03K 17/12 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7819 (2013.01); H01L 21/28035 (2013.01); H01L 21/761 (2013.01); H01L 27/0727 (2013.01); H01L 29/0646 (2013.01); H01L 29/0847 (2013.01); H01L 29/1095 (2013.01); H01L 29/4916 (2013.01); H01L 29/66136 (2013.01); H01L 29/66659 (2013.01); H01L 29/66681 (2013.01); H01L 29/7835 (2013.01); H01L 29/7838 (2013.01); H03K 17/122 (2013.01); H03K 17/687 (2013.01); H01L 29/1083 (2013.01); H01L 29/42368 (2013.01);
Abstract

A device includes a laterally diffused MOSFET, which in turn includes n-type source and drain regions in a p-type semiconductor substrate. A gate electrode is located over the semiconductor substrate between the source region and the drain region. An isolation region is laterally spaced apart from the source region, and is bounded by an n-type buried layer and an n-type well region that reaches from a surface of the substrate to the buried layer. A p-type doped region and an n-type doped region are disposed within the isolation region, the p-type doped region and the n-type doped region forming a diode. A first conductive path connects the n-type doped region to the source region, and a second conductive path connects the p-type doped region to the gate electrode.


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