The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

May. 14, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Hsiao-Chun Chang, Hsinchu County, TW;

Guan-Jie Shen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6681 (2013.01); H01L 21/265 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 29/0653 (2013.01); H01L 29/785 (2013.01);
Abstract

A method of forming a semiconductor device includes following steps. A semiconductor strip is formed extending above a semiconductor substrate. A shallow trench isolation (STI) region is formed over the semiconductor substrate. The semiconductor strip has a fin structure higher than a top surface of the STI region. The fin structure includes a channel portion and a source/drain (S/D) portion adjacent to the channel portion. A dummy gate stack is formed over the channel portion. The S/D portion is exposed by the dummy gate stack. A doping process is performed to a top of the S/D portion using first dopants. An epitaxy layer is formed around the top of the S/D portion. The epitaxy layer has second dopants. A conductivity type of the second dopants is different from a conductivity type of the first dopants. The dummy gate stack is replaced with a replacement gate stack.


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