The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Dec. 18, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

Chandramouleeswaran Subramani, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); G06F 13/10 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 24/16 (2013.01); G06F 13/102 (2013.01); H01L 23/3157 (2013.01); H01L 24/13 (2013.01); H01L 24/81 (2013.01); H01L 25/18 (2013.01); H01L 21/563 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/13026 (2013.01); H01L 2224/13109 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13113 (2013.01); H01L 2224/13118 (2013.01); H01L 2224/13124 (2013.01); H01L 2224/13138 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16157 (2013.01); H01L 2224/16503 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/8112 (2013.01); H01L 2224/81193 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/92125 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01032 (2013.01);
Abstract

An apparatus, comprising an integrated circuit (IC) package having at least one solder bond pad, a die having at least one solder bond pad, wherein the die is bonded to the IC package by at least one solder joint between the at least one solder bond pad of the die, and the at least one solder bond pad of the IC package, and an underfill material between the IC package and the die, wherein the at least one solder joint is embedded in the underfill material, and wherein the at least one solder joint comprises a first metallurgy and a second metallurgy.


Find Patent Forward Citations

Subramani, Chandramouleeswaran. (2022). Dual solder methodologies for ultrahigh density first level interconnections (U.S. Patent No. 11322469). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11322469

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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