The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Oct. 01, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Julie Yang, Hsin-Chu, TW;

Chii-Ming Wu, Taipei, TW;

Tzu-Chung Tsai, Hsinchu County, TW;

Yao-Wen Chang, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 24/03 (2013.01); H01L 24/13 (2013.01); H01L 2224/02206 (2013.01); H01L 2224/02215 (2013.01); H01L 2224/03019 (2013.01); H01L 2224/03614 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/13026 (2013.01); H01L 2924/04941 (2013.01); H01L 2924/05432 (2013.01);
Abstract

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of bond pad structures over an interconnect structure on a front-side of a semiconductor body. The plurality of bond pad structures respectively have a titanium contact layer. The interconnect structure and the semiconductor body are patterned to define trenches extending into the semiconductor body. A dielectric fill material is formed within the trenches. The dielectric fill material is etched to expose the titanium contact layer prior to bonding the semiconductor body to a carrier substrate. The semiconductor body is thinned to expose the dielectric fill material along a back-side of the semiconductor body and to form a plurality of integrated chip die. The dielectric fill material is removed to separate the plurality of integrated chip die.


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