The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Apr. 09, 2020
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Amey Mahadev Walke, Heverlee, BE;

Niamh Waldron, Heverlee, BE;

Nadine Collaert, Blanden, BE;

Ming Zhao, Bertem, BE;

Assignee:

IMEC vzw, Leuven, BE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76256 (2013.01); H01L 25/16 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/4236 (2013.01);
Abstract

The disclosed technology relates generally to the field of semiconductor devices, and more particularly to co-integration of GaN-based devices with Si-based devices. In one aspect, a method of forming a semiconductor device includes forming a first wafer including, on a front side thereof, a III-V semiconductor layer stack formed on a first substrate and a first bonding layer. The III-V semiconductor layer stack includes a GaN-based device layer structure formed on the first substrate. The method additionally includes, subsequent to forming the first wafer, bonding the first bonding layer to a second bonding layer of a second wafer. The second wafer includes a second silicon substrate supporting an active device layer, a back-end-of-line interconnect structure and the second bonding layer. The method further comprises, subsequent to bonding, thinning the first wafer from a backside, wherein thinning includes removing at least the first substrate. In another aspect, a semiconductor device includes a cointegrated N-polar HEMT.


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