The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Dec. 14, 2020
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Vivek Raj, Bangalore, IN;

Shivraj G. Dharne, Bangalore, IN;

Uttam K. Saha, San Jose, CA (US);

Mahbub Rashed, Cupertino, CA (US);

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 11/418 (2006.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 11/412 (2013.01); G11C 11/418 (2013.01);
Abstract

A single-rail memory circuit includes an array of memory cells arranged in rows and columns and peripheral circuitry connected to the array for facilitating read and write operations with respect to selected memory cells. The peripheral circuitry includes, but is not limited to, boost circuits for the rows. Each boost circuit is connected to a wordline for a row and to a discrete voltage supply line for the same row. Each boost circuit for a row is configured to increase the voltage levels on the wordline and the voltage supply line for the row during a read of any selected memory cell within the row. Increasing the voltage levels on the wordline and on the voltage supply line during the read operation effectively boosts the read current. A method of operating the memory circuit reduces the probability of a read fail.


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