The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2022
Filed:
Feb. 28, 2020
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Masaru Morohashi, Hachioji, JP;
Hidekazu Noguchi, Shinjuku-ku, JP;
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G11C 11/406 (2006.01); G11C 15/04 (2006.01); G11C 8/10 (2006.01); G06F 13/16 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40615 (2013.01); G06F 13/1636 (2013.01); G11C 8/10 (2013.01); G11C 11/40611 (2013.01); G11C 11/40622 (2013.01); G11C 15/04 (2013.01); G11C 16/349 (2013.01);
Abstract
An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.