The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Jun. 18, 2020
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Naveen Kumar, San Jose, CA (US);

Aman Bhatia, San Jose, CA (US);

Chenrong Xiong, San Jose, CA (US);

Yu Cai, San Jose, CA (US);

Fan Zhang, Fremont, CA (US);

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G11C 29/52 (2006.01); H03M 13/37 (2006.01); H03M 13/45 (2006.01); H03M 13/11 (2006.01); H03M 13/13 (2006.01); H03M 13/29 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1076 (2013.01); G06F 11/1012 (2013.01); G11C 29/52 (2013.01); H03M 13/1111 (2013.01); H03M 13/13 (2013.01); H03M 13/293 (2013.01); H03M 13/2906 (2013.01); H03M 13/2948 (2013.01); H03M 13/3746 (2013.01); H03M 13/45 (2013.01); G11C 2029/0411 (2013.01);
Abstract

Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when reading data from a superblock of the memory, where the decoding of multiple wordlines failed, a computer system schedules the decoding of failed wordlines based on quantity of bit errors and updates soft information based on convergence or divergence of the scheduled decoding. Such a computer system significantly reduces decoding failures associated with data reads from the memory and allows improved data retention in the memory.


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