The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2022

Filed:

Nov. 12, 2020
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Wein-Town Sun, Hsinchu County, TW;

Chun-Hsiao Li, Hsinchu County, TW;

Assignee:

EMEMORY TECHNOLOGY INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); H01L 29/06 (2006.01); H01L 29/792 (2006.01); G11C 16/34 (2006.01); H01L 29/423 (2006.01); G11C 16/04 (2006.01); H01L 27/11563 (2017.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H01L 27/11524 (2017.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0653 (2013.01); G11C 16/0425 (2013.01); G11C 16/0466 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/34 (2013.01); H01L 27/11524 (2013.01); H01L 27/11563 (2013.01); H01L 29/4234 (2013.01); H01L 29/7885 (2013.01); H01L 29/792 (2013.01);
Abstract

An erasable programmable non-volatile memory includes a first-type well region, three doped regions, two gate structures, a blocking layer and an erase line. The first doped region is connected with a source line. The third doped region is connected with a bit line. The first gate structure is spanned over an area between the first doped region and the second doped region. A first polysilicon gate of the first gate structure is connected with a select gate line. The second gate structure is spanned over an area between the second doped region and the third doped region. The second gate structure includes a floating gate and the floating gate is covered by the blocking layer. The erase line is contacted with the blocking layer. The erase line is located above an edge or a corner of the floating gate.


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