The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2022

Filed:

May. 27, 2020
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Shih-Chieh Lin, Puzi, TW;

Shuen-Hsiang Ke, Changhua, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8242 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10885 (2013.01); H01L 27/10897 (2013.01);
Abstract

A method for forming a memory structure includes: providing a substrate including a memory array region and a peripheral circuit region; forming a plurality of bit line structures in the memory array region; forming a dielectric layer in the peripheral circuit region; forming a plurality of contacts between the bit line structures; depositing a protective layer on the substrate; depositing a hard mask layer on the protective layer; etching back the hard mask layer to form a hard mask spacer on the first top surface of the protective layer and immediately adjacent to the peripheral circuit region; and etching the protective layer with the hard mask spacer as an etching mask to leave a protective feature at the boundary between the memory array region and the peripheral circuit region.


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Lin, Shih-Chieh. (2022). Memory structure and method for forming the same (U.S. Patent No. 11315932). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11315932

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