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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11315922 B1

PDFFull Text
Date of Patent:
Apr. 26, 2022

Filed:

Mar. 03, 2020

Fin cut to prevent replacement gate collapse on sti

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Andrew M. Greene, Slingerlands, NY (US);

Balasubramanian Pranatharthiharan, Watervliet, NY (US);

Sivananda K. Kanakasabapathy, Pleasanton, CA (US);

John R. Sporre, Albany, NY (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

Robert Sullivan

Michael J. Chang, LLC

Primary Examiner:

Joseph C Nicely

Assistant Examiner:

Lamont B Koo

Int. Cl.
CPC ...
H01L 29/165 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 21/823878 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7842 (2013.01); H01L 29/7851 (2013.01);
Abstract

The present invention provides fin cut techniques in a replacement gate process for finFET fabrication. In one aspect, a method of forming a finFET employs a dummy gate material to pin a lattice constant of patterned fins prior to a fin cut thereby preventing strain relaxation. A dielectric fill in a region of the fin cut (below the dummy gates) reduces an aspect ratio of dummy gates formed from the dummy gate material in the fin cut region, thereby preventing collapse of the dummy gates. FinFETs formed using the present process are also provided.

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