The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 2022
Filed:
Feb. 16, 2018
Applicant:
Nexperia B.v., Nijmegen, NL;
Inventors:
Wolfgang Schnitt, Hamburg, DE;
Tobias Sprogies, Hamburg, DE;
Assignee:
Nexperia B.V., Nijmegen, NL;
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 25/065 (2006.01); H01L 23/538 (2006.01); H01L 23/29 (2006.01); H01L 25/00 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3114 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/291 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/94 (2013.01);
Abstract
The disclosure relates to chips scale packages and methods of forming such packages or an array of such packages. The semiconductor chip scale package comprises: a semiconductor die, comprising: a first major surface opposing a second major surface; a plurality side walls extending between the first major surface and the second major surface; a plurality of electrical contacts arranged on the second major surface of the semiconductor die; and an inorganic insulating material arranged on the plurality of side walls and on the first major surface.