The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2022

Filed:

Sep. 03, 2019
Applicant:

Kla Corporation, Milpitas, CA (US);

Inventors:

Farhat A. Quli, Milpitas, CA (US);

Andrew Nguyen, San Jose, CA (US);

James Richard Bella, San Jose, CA (US);

Assignee:

KLA Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); H05K 1/18 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67253 (2013.01); H01L 21/67248 (2013.01); H05K 1/023 (2013.01); H05K 1/181 (2013.01); H05K 2201/10151 (2013.01);
Abstract

A process condition measurement wafer assembly is disclosed. In embodiments, the process condition measurement wafer assembly includes a bottom substrate and a top substrate. In another embodiment, the process condition measurement wafer assembly includes one or more electronic components disposed on one or more printed circuit elements and interposed between the top substrate and bottom substrate. In another embodiment, the process condition measurement wafer assembly includes one or more shielding layers formed between the bottom substrate and the top substrate. In embodiments, the one or more shielding layers are configured to electromagnetically shield the one or more electronic components and diffuse voltage potentials across the bottom substrate and the top substrate.


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