The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2022

Filed:

Feb. 23, 2021
Applicant:

Realtek Semiconductor Corp., Hsinchu, TW;

Inventors:

Shih-Han Lin, Hsinchu, TW;

Chun-Chi Yu, Hsinchu, TW;

Chih-Wei Chang, Hsinchu, TW;

Gerchih Chou, San Jose, CA (US);

Shih-Chang Chen, Hsinchu, TW;

Kuo-Wei Chi, Hsinchu, TW;

Fu-Chin Tsai, Hsinchu, TW;

Min-Han Tsai, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/50 (2006.01); G11C 11/401 (2006.01);
U.S. Cl.
CPC ...
G11C 29/50004 (2013.01); G11C 11/401 (2013.01);
Abstract

A detection circuit and a detection method are provided. The detection circuit is suitable for a system-on-chip (SoC). The SoC is coupled to an alarm pin of a DDR4 memory through a connection pad, and the detection circuit includes a control circuit coupled to the connection pad. In response to the DDR4 memory performing a refresh process or a specific event occurring, the control circuit outputs a test signal with a first voltage level to the connection pad, and determines whether a voltage level of the connection pad is tied to a second voltage level. In response to determining that the voltage level of the connection pad is tied to the second voltage level, the control circuit outputs an interrupt signal to a CPU of the SoC, and the interrupt signal indicates that the alarm pin of the DDR4 memory is not controlled normally by the DDR4 memory.


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