Hardware for supporting time triggered load anticipation in the context of a real time os

Abstract

An integrated circuit is disclosed that includes a central processing unit (CPU), a random access memory (RAM) configured for storing data and CPU executable instructions, a first peripheral circuit for accessing memory that is external to the integrated circuit, a second peripheral circuit, and a communication bus coupled to the CPU, the RAM, the first peripheral circuit and the second peripheral circuit. The second peripheral circuit includes a first preload register configured to receive and store a first preload value, a first register configured to store first information that directly or indirectly identifies a first location where first instructions of a first task can be found in memory that is external to the integrated circuit, and a counter circuit that includes a counter value. The counter circuit can increment or decrement the counter value with time when the counter circuit is started. A first compare circuit is also included and can compare the counter value to the first preload value. The first compare circuit is configured to assert a first match signal in response to detecting a match between the counter value and the first preload value. The second peripheral circuit is configured to send a first preload request to the first peripheral circuit in response to an assertion of the first match signal. The first preload request identifies the location where the first instructions of the first task can be found in the external memory.