The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2022

Filed:

Jun. 25, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Johnny A. Lam, Firestone, CO (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/1009 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0655 (2013.01); G06F 3/061 (2013.01); G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 12/1009 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/7201 (2013.01);
Abstract

A processing device includes a system tag data structure to store a system tag that includes a logical transfer unit (LTU) identifier corresponding to an LTU, which includes a subset of a plurality of sequential logical block addresses (LBAs) that includes an LBA of a read request, and a mapping data structure that maps a zone of LBA space to physical address space. Hardware logic is to: retrieve the LTU identifier from the system tag; determine a zone identifier (ID) based on the LTU identifier; index, using at least one of the zone ID or the LTU identifier, into the mapping data structure to retrieve metadata that specifies a mapping between the LTU identifier and a physical address of the physical address space; and store the metadata in the system tag data structure in association with the system tag.


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