The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2022

Filed:

Oct. 04, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Wei Bing Shang, Shanghai, CN;

Yu Zhang, Shanghai, CN;

Hong Wen Li, Shanghai, CN;

Yu Peng Fan, Shanghai, CN;

Zhong Lai Liu, Shanghai, CN;

En Peng Gao, Shanghai, CN;

Liang Zhang, Shanghai, CN;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/45 (2006.01); H03M 13/00 (2006.01); G06F 11/10 (2006.01); G06F 11/00 (2006.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
H03M 13/45 (2013.01); G06F 9/38 (2013.01); G06F 11/1048 (2013.01); H03M 13/611 (2013.01);
Abstract

Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.


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