The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2022
Filed:
Mar. 18, 2020
Applicant:
Winbond Electronics Corp., Taichung, TW;
Inventors:
Yi-Hui Chen, Taichung, TW;
Chih-Hao Lin, Taichung, TW;
Assignee:
Winbond Electronics Corp., Taichung, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 21/764 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/788 (2013.01); H01L 21/764 (2013.01); H01L 29/4991 (2013.01); H01L 29/515 (2013.01); H01L 29/66825 (2013.01);
Abstract
A non-volatile memory structure including a substrate, a plurality of charge storage layers, a first dielectric layer, and a control gate is provided. The charge storage layers are located on the substrate. An opening is provided between two adjacent charge storage layers. The first dielectric layer is located on the charge storage layers and on a surface of the opening. A bottom cross-sectional profile of the first dielectric layer located in the opening is a profile that is recessed on both sides. The control gate is located on the first dielectric layer and fills the opening.