The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2022

Filed:

Mar. 16, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Violante Moschiano, Avezzano, IT;

Tecla Ghilardi, Trescore B., IT;

Tommaso Vali, Sezze, IT;

Emilio Camerlenghi, Bergamo, IT;

William C. Filipiak, Boise, ID (US);

Andrea D'Alessandro, L'Aquila, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/26 (2006.01); G11C 8/08 (2006.01); G11C 11/413 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3404 (2013.01); G11C 5/063 (2013.01); G11C 8/08 (2013.01); G11C 11/413 (2013.01); G11C 16/26 (2013.01);
Abstract

Memories having a controller configured, during a pre-charge portion of a read operation, to apply a sequence of increasing voltage levels concurrently to each access line of a plurality of access lines, wherein each voltage level of the sequence of increasing voltage levels is higher than any previous voltage level of the sequence of increasing voltage levels and lower than any subsequent voltage level of the sequence of increasing voltage levels, and determine a particular voltage level of the sequence of increasing voltage levels corresponding to a point at which all memory cells of the plurality of strings of series-connected memory cells are first deemed to be activated while applying the sequence of increasing voltage levels.


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