The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2022

Filed:

May. 28, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chung-Chieh Yang, Hsinchu County, TW;

Tai-Yi Chen, Hsinchu County, TW;

Yun-Ru Chen, Keelung, TW;

Yung-Chow Peng, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/392 (2020.01); G06F 30/367 (2020.01); G06F 30/3953 (2020.01); G06F 30/373 (2020.01); G06F 119/06 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/367 (2020.01); G06F 30/392 (2020.01); G06F 30/3953 (2020.01); G06F 30/373 (2020.01); G06F 2119/06 (2020.01);
Abstract

A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; and when the circuit design meets the predetermined specification, generating a power delivery network layout of the integrated circuit, and generating, after the power delivery network layout is generated, a circuit layout of the integrated circuit.


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