The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2022

Filed:

Mar. 27, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Byoungchan Oh, Hillsboro, OR (US);

Sai Dheeraj Polagani, Hillsboro, OR (US);

Joshua B. Fryman, Corvallis, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 12/0879 (2016.01); G11C 11/4093 (2006.01); G11C 5/04 (2006.01); G11C 29/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G06F 12/0879 (2013.01); G06F 13/4239 (2013.01); G11C 5/04 (2013.01); G11C 11/4093 (2013.01); G11C 29/42 (2013.01); G11C 2207/2254 (2013.01);
Abstract

An apparatus is described. The apparatus includes a rank of memory chips to couple to a memory channel. The memory channel is characterized as having eight transfers of eight bits of raw data per burst access. The rank of memory chips has first, second and third X4 memory chips. The X4 memory chips conform to a JEDEC dual data rate (DDR) memory interface specification. The first and second X4 memory chips are to couple to an eight bit raw data portion of the memory channel's data bus. The third X4 memory chip to couple to an error correction coding (ECC) information portion of the memory channel's data bus.


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