The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2022

Filed:

Nov. 30, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sarathy Jayakumar, Portland, OR (US);

Ashok Raj, Portland, OR (US);

Wei P. Chen, Portland, OR (US);

Theodros Yigzaw, Sherwood, OR (US);

John Holm, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/1027 (2016.01); G06F 12/0864 (2016.01); G06F 13/16 (2006.01); G06F 11/22 (2006.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 12/1027 (2013.01); G06F 9/384 (2013.01); G06F 9/3806 (2013.01); G06F 11/2284 (2013.01); G06F 12/0864 (2013.01); G06F 13/1673 (2013.01); G06F 13/1694 (2013.01);
Abstract

In an embodiment, a processor for reverse translation includes a plurality of processing engines (PEs) to execute threads and a reverse translation circuit. The reverse translation circuit is to: determine a target module address of a corrupt portion of a memory module; determine a plurality of system physical address (SPA) addresses associated with the memory module; and for each SPA address in the plurality of SPA addresses, translate the SPA address into a translated module address, and in response to a determination that the translated module address matches the target module address, log the SPA address as a result of a reverse translation of the target module address. Other embodiments are described and claimed.


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