The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

Sep. 10, 2020
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Yan Fei Cai, Shanghai, CN;

Kai Hua Hou, Shanghai, CN;

Yuan Chai, Shanghai, CN;

Jian Chen, Shanghai, CN;

Jun Wang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/037 (2006.01); H03K 3/012 (2006.01); H03K 3/3562 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0372 (2013.01); H03K 3/012 (2013.01); H03K 3/3562 (2013.01);
Abstract

A flip-flop is provided. The flip-flop includes: a first inverter including an input terminal to receive data signal and an output terminal coupled to an input terminal of the master latch, a second inverter, a master latch including an output terminal coupled to an input terminal of a slave latch, and the slave latch including an output terminal coupled to an input terminal of the second inverter. An output terminal of the second inverter is configured as an output terminal of the flip-flop. A duration of the first clock signal inputted to the master latch is greater than a duration of the first clock signal inputted to the slave latch. A duration of the second clock signal inputted to the master latch is greater than a duration of the second clock signal inputted to the slave latch.


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