The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

Feb. 26, 2020
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventor:

Jin Yong Oh, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/48 (2006.01); H01L 27/11573 (2017.01); H01L 27/11575 (2017.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/76224 (2013.01); H01L 23/481 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01);
Abstract

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a slit structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the slit structure. The 3D memory device further includes an insulating structure extending vertically from the second side of the substrate to the first doped region. The 3D memory device further includes a plurality of second doped regions in the substrate and separated by the insulating structure.


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