The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

Oct. 04, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ekmini Anuja De Silva, Slingerlands, NY (US);

Ashim Dutta, Menands, NY (US);

Praveen Joseph, Albany, NY (US);

Nelson Felix, Slingerlands, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76829 (2013.01); H01L 21/76843 (2013.01); H01L 21/76897 (2013.01); H01L 23/5226 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01);
Abstract

A method of forming a semiconductor structure includes forming one or more interconnect lines, the one or more interconnect lines including trenches of a first metal material surrounded by a first interlayer dielectric layer. The method also includes forming pillars of a second metal material different than the first metal material over the one or more interconnect lines utilizing a metal on metal growth process, and forming an etch stop dielectric layer, the pillars of the second metal material shaping the etch stop dielectric layer. The method further includes forming one or more vias to the one or more interconnect lines, the one or more vias being fully aligned to the one or more interconnect lines using the etch stop dielectric layer.


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