The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

Jan. 25, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventor:

Hsiang-Wei Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 27/1157 (2017.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 21/3213 (2006.01); H01L 21/033 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76802 (2013.01); H01L 21/0337 (2013.01); H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01);
Abstract

A method for forming an interconnect structure is provided. The method for an interconnect structure includes forming a first metal material over a semiconductor substrate, and forming a first mask element over the first metal material. The first mask element has an opening through the first mask element. The method for forming the interconnect structure also includes forming a second metal material over the first mask element and the first metal material and in the opening, and forming a second mask element corresponding to the opening and over the second metal material. The method for forming the interconnect structure also includes etching the second metal material and the first metal material using the second mask element and the first mask element to form a via and a first metal line respectively.


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