The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

Apr. 13, 2020
Applicant:

Lam Research Corporation, Fremont, CA (US);

Inventors:

Anthony J. Ricci, Sunnyvale, CA (US);

Keith Comendant, Fremont, CA (US);

James Tappan, Fremont, CA (US);

Assignee:

LAM RESEARCH CORPORATION, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/683 (2006.01); H05B 3/26 (2006.01); H01L 21/67 (2006.01); H01J 37/32 (2006.01);
U.S. Cl.
CPC ...
H01L 21/6833 (2013.01); H01J 37/32724 (2013.01); H01L 21/67103 (2013.01); H01L 21/6831 (2013.01); H05B 3/26 (2013.01); H01J 2237/20 (2013.01); H01L 2221/683 (2013.01); Y10T 29/49146 (2015.01); Y10T 29/53252 (2015.01); Y10T 279/23 (2015.01);
Abstract

A substrate support for control of a temperature of a semiconductor substrate supported thereon during plasma processing of the semiconductor substrate includes a temperature-controlled base having a top surface, a metal plate, and a film heater. The film heater is a thin and flexible polyimide heater film with a plurality of independently controlled resistive heating elements thermally coupled to an underside of the metal plate. The film heater is electrically insulated from the metal plate. A first layer of adhesive bonds the metal plate and the film heater to the top surface of the temperature-controlled base. A layer of dielectric material is bonded to a top surface of the metal plate with a second layer of adhesive. The layer of dielectric material forms an electrostatic clamping mechanism for supporting the semiconductor substrate.


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