The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

Nov. 13, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Jing Sha, White Plains, NY (US);

Martin Burkhardt, White Plains, NY (US);

Sean Burns, Hopewell Junction, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06T 7/11 (2017.01); G06N 3/04 (2006.01); G06N 3/08 (2006.01); G06T 7/00 (2017.01); G06T 7/174 (2017.01); G06V 20/10 (2022.01); G06K 9/62 (2022.01);
U.S. Cl.
CPC ...
G06N 3/04 (2013.01); G06N 3/08 (2013.01); G06T 7/0004 (2013.01); G06T 7/11 (2017.01); G06T 7/174 (2017.01); G06V 20/176 (2022.01); G06K 9/6218 (2013.01); G06T 2207/20081 (2013.01); G06T 2207/20084 (2013.01); G06T 2207/30148 (2013.01);
Abstract

According to one or more embodiments of the present invention a computer-implemented method for fabricating a chip includes generating, using an aerial image generation system, a set of aerial images for a chip layout, the set of aerial images including an aerial image corresponding to each region from the chip layout. The method further includes automatically determining, using an artificial neural network, a feature vector for each aerial image from the set of aerial images. The method further includes clustering the aerial images using their corresponding feature vectors. The method further includes selecting, as test samples, a predetermined number of aerial images from each cluster. The method further includes performing a pattern coverage inspection of the chip layout using the aerial images that are selected as test samples.


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