The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

May. 16, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jawad B. Khan, Portland, OR (US);

Shigeki Tomishima, Portland, OR (US);

Srikanth Srinivasan, Portland, OR (US);

Chetan Chauhan, Folsom, CA (US);

Rajesh Sundaram, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); H03M 13/29 (2006.01); H03M 13/00 (2006.01); G06F 3/00 (2006.01); G11C 7/10 (2006.01); G06F 11/10 (2006.01); G06N 3/08 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0604 (2013.01); G06F 3/0653 (2013.01); G06F 3/0673 (2013.01); G06F 11/1076 (2013.01); G06N 3/08 (2013.01); G11C 7/1051 (2013.01); G11C 7/1096 (2013.01); H03M 13/2906 (2013.01);
Abstract

Technologies for providing multiple tier memory media management include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory compute operation. Additionally, the media access circuitry is to read, in response to the request, data from a memory media region of the memory media, write the read data into a compute media region of the memory, perform, on the data in the compute media region, the in-memory compute operation, write, to the memory media region, resultant data indicative of a result of performance of the in-memory compute operation.


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