The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2022

Filed:

Sep. 18, 2020
Applicant:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Inventors:

Li-Peng Chang, Hsinchu, TW;

San-Jung Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/764 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10885 (2013.01); H01L 21/7682 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01); H01L 27/10855 (2013.01); H01L 27/10876 (2013.01);
Abstract

Provided is a dynamic random access memory (DRAM) including a substrate, a plurality of word-line sets, a plurality of bit-line structures, a plurality of capacitors, a plurality of capacitor contacts, and a plurality of air gaps. The substrate has a plurality of active areas. The word-line sets extend along a Y direction and disposed in the substrate. The bit-line structures extend along a X direction, disposed on the substrate, and across the word-line sets. The capacitors are respectively disposed at two terminals of the active areas. The capacitor contacts are respectively disposed between the capacitors and the active regions. The air gaps are disposed in a plurality of spaces enclosed by the bit-line structures and the capacitor contacts. A method of forming a DRAM is also provided.


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